View AD8557_253278.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Digitally Programmable Sensor Signal Amplifier www..com
Preliminary Technical Data
FEATURES
Very low offset voltage: 10 V max over temperature Very low input offset voltage drift: 50 nV/C max High CMRR: 96 dB min Digitally programmable gain and output offset voltage Gain Range from 28 to 1300 Single-wire serial interface Stable with any capacitive load SOIC_N and LFCSP_VQ packages 2.7 V to 5.5 V operation
AD8557
APPLICATIONS
Automotive sensors Pressure and position sensors Precision current sensing Thermocouple amplifiers Industrial weigh scales Strain gages
FUNCTIONAL BLOCK DIAGRAM
VDD VDD VNEG A1 VSS R1 VDD VSS P1 R3 P2 VSS R2 R5 A2 VPOS VDD VSS DAC P4 R7 A3 VOUT R4 P3 R6 VCLAMP A4
VDD
VSS Figure 1.
Rev.PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2006 Analog Devices, Inc. All rights reserved.
AD8557 TABLE OF CONTENTS
Specifications..................................................................................... 4 Absolute Maximum Ratings....... Error! Bookmark not defined. Thermal Resistance ................. Error! Bookmark not defined. ESD Caution............................. Error! Bookmark not defined. Pin Configurations and Function Descriptions ........................... 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 10
Preliminary Technical Data
www..com
Gain Values ................................................................................. 11 Open Wire Fault Detection....................................................... 12 Shorted Wire Fault Detection................................................... 12 Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 12 Device Programming................................................................. 12 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
XXXX--Revision 0: Initial Version
Rev. PrC | Page 2 of 19
Preliminary Technical Data GENERAL DESCRIPTION
The AD8557 is a zero-drift, sensor signal amplifier with digitally programmable gain and output offset. Designed to easily and accurately convert variable pressure sensor and strain bridge outputs to a well-defined output voltage range, the AD8557 accurately amplifies many other differential or singleended sensor outputs. The AD8557 uses the ADI patented low noise auto-zero and DigiTrim(R) technologies to create an incredibly accurate and flexible signal processing solution in a very compact footprint. Gain is digitally programmable in a wide range from 28 to 1300 through a serial data interface. Gain adjustment can be fully simulated in-circuit and then permanently programmed with reliable polyfuse technology. Output offset voltage is also digitally programmable and is ratiometric to the supply voltage. When used in conjunction with an ADC referenced to the same supply, the system accuracy becomes immune to normal supply voltage variations. Output offset voltage can be adjusted with a resolution of better than 0.4% of the difference between VDD
AD8557
www..com
and VSS. A lockout trim after gain and offset adjustment further ensures field reliability. In addition to extremely low input offset voltage and input offset voltage drift and very high dc and ac CMRR, the AD8557 also includes a pull-up current source at the input pins and a pull-down current source at the VCLAMP pin. Output clamping set via an external reference voltage allows the AD8557 to drive lower voltage ADCs safely and accurately. When used in conjunction with an ADC referenced to the same supply, the system accuracy becomes immune to normal supply voltage variations. Output offset voltage can be adjusted with a resolution of better than 0.4% of the difference between VDD and VSS. A lockout trim after gain and offset adjustment further ensures field reliability. The AD8557 is fully specified from -40C to +125C. Operating from single-supply voltages of 2.7 V to 5.5 V, the AD8557 is offered in the 8-lead SOIC_N, and 4 mm x 4 mm 16-lead LFCSP_VQ.
Rev. PrC | Page 3 of 19
AD8557 SPECIFICATIONS
Preliminary Technical Data
www..com
VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, Gain = 28, TA = 25C, unless otherwise specified. Table 1. Electrical Specifications
Parameter INPUT STAGE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Linearity Differential Gain Accuracy Differential Gain Accuracy Differential Gain Temperature Coefficient DAC Accuracy Ratiometricity Output Offset Temperature Coefficient VCLAMP Input Bias Current Input Voltage Range OUTPUT STAGE Short-Circuit Current Output Voltage, Low Output Voltage, High POWER SUPPLY Supply Current Power Supply Rejection Ratio DYNAMIC PERFORMANCE Gain Bandwidth Product Settling Time NOISE PERFORMANCE Input Referred Noise Low Frequency Noise Total Harmonic Distortion DIGITAL INTERFACE Input Current DIGIN Pulse Width to Load 0 DIGIN Pulse Width to Load 1 Time Between Pulses at DIGIN DIGIN Low DIGIN High DIGOUT Logic 0 Symbol VOS TCVOS IB IOS CMRR Conditions -40C TA +125C -40C TA +125C -40C TA +125C VCM = 0.9 V to 3.6 V, AV = 28 VCM = 0.9 V to 3.6 V, AV = 1300 VO = 0.2 V to 3.4 V VO = 0.2 V to 4.8 V Second stage gain = 10 to 70 Second stage gain = 100 to 250 Second stage gain = 10 to 250 Offset codes = 8 to 248 Offset codes = 8 to 248 Offset codes = 8 to 248 8 0.8 70 96 Min Typ 2 18 1 82 112 20 1000 1.6 2.5 15 0.7 50 5 20 100 1.25 Source Sink RL = 10 k to 5 V RL = 10 k to 0 V VO = 2.5 V, VPOS = VNEG = 2.5 V, VDAC code = XXXX -40C TA +125C GBP ts First gain stage Second gain stage To 0.1%, 4 V output step f = 1 kHz f = 0.1 Hz to 10 Hz VIN = 16.75 mV rms, f = 1 kHz 105 2 8 8 32 0.5 -100 2 tw0 tw1 tws 0.05 50 10 4 1
Rev. PrC | Page 4 of 19
Max 10 50 28 8 3.6
Unit V nV/C nA nA V dB dB ppm ppm % % ppm/C % ppm mV ppm FS/C nA V mA mA mV V
40 0.8 35 80 330 2.64 -25 30
ICLAMP
166
ISC ISC VOL VOH ISY PSRR
40 4.94
-40 50
1.8 125
mA dB
MHz MHz s nV/Hz V p-p dB A s s s V V V
en p-p THD
10
1
Preliminary Technical Data
Parameter DIGOUT Logic 1 Symbol Conditions Min 4 Typ
AD8557
www..com
Max
Unit V
VDD = 2.7 V, VSS = 0.0 V, VCM = 1.35 V, VO = 1.35 V, Gain = 28, TA = 25C, unless otherwise specified. Table 2. Electrical Specifications
Parameter INPUT STAGE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Linearity Differential Gain Accuracy Differential Gain Temperature Coefficient DAC Accuracy Ratiometricity Output Offset Temperature Coefficient VCLAMP Input Bias Current Input Voltage Range OUTPUT STAGE Short-Circuit Current Output Voltage, Low Output Voltage, High POWER SUPPLY Supply Current Power Supply Rejection Ratio DYNAMIC PERFORMANCE Gain Bandwidth Product Settling Time NOISE PERFORMANCE Input Referred Noise Low Frequency Noise Total Harmonic Distortion DIGITAL INTERFACE Input Current DIGIN Pulse Width to Load 0 DIGIN Pulse Width to Load 1 Time Between Pulses at DIGIN DIGIN Low DIGIN High DIGOUT Logic 0 DIGOUT Logic 1 Symbol VOS TCVOS IB IOS CMRR Conditions -40C TA +125C -40C TA +125C -40C TA +125C VCM = 0.9 V to 3.6 V, AV = 28 VCM = 0.9 V to 3.6 V, AV = 1300 VO = 0.2 V to 3.4 V VO = 0.2 V to 4.8 V Second stage gain = 10 to 250 Second stage gain = 10 to 250 Offset codes = 8 to 248 Offset codes = 8 to 248 Offset codes = 8 to 248 8 0.5 70 96 Min Typ 2 18 0.2 82 112 20 1000 1.6 15 0.7 50 5 20 100 1.25 Source Sink RL = 10 k to 5 V RL = 10 k to 0 V VO = 2.5 V, VPOS = VNEG = 2.5 V, VDAC code = XXXX -40C TA +125C GBP ts First gain stage Second gain stage To 0.1%, 4 V output step f = 1 kHz f = 0.1 Hz to 10 Hz VIN = 16.75 mV rms, f = 1 kHz 105 2 8 8 32 0.5 -100 2 tw0 tw1 tws 0.05 50 10 4 1 4
Rev. PrC | Page 5 of 19
Max 10 50 28 1 1.6
Unit V nV/C nA nA V dB dB ppm ppm % ppm/C % ppm mV ppm FS/C nA V mA mA mV V
40 0.8 35 80 330 2.64 -7 30
ICLAMP
166
ISC VOL VOH ISY PSRR
15 2.64
-12 20
1.8 125
mA dB
MHz MHz s nV/Hz V p-p dB A s s s V V V V
en p-p THD
10
1
AD8557 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage Input Voltage Differential Input Voltage1 Output Short-Circuit Duration to VSS or VDD ESD (Human Body Model) Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature Range
1
Preliminary Technical Data
www..com
Rating 6V VSS - 0.3 V to VDD + 0.3 V 5.0 V Indefinite 2000 V -65C to +150C -40C to +125C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type 8-Lead SOIC_N (R) 16-Lead LFCSP_VQ (CP)
1
Differential input voltage is limited to 5.0 V or the supply voltage, whichever is less.
JA1 158 44
JC 43 31.5
Unit C/W C/W
JA is specified for the worst-case conditions, that is, JA is specified for device soldered in circuit board for LFCSP_VQ package.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrC | Page 6 of 19
Preliminary Technical Data PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DVDD
16 AVDD
AD8557
www..com
VDD 1 DIGOUT 2 DIGIN 3 VNEG 4
8
VSS VOUT VCLAMP VPOS
05448-002
14 AVSS
AD8557
TOP VIEW
7 6 5
NC 1 DIGOUT 2 NC 3 DIGIN 4
PIN 1 INDICATOR
15
13
DVSS
12 VOUT 11
AD8557
TOP VIEW
NC NC
10 VCLAMP 9
Figure 2. 8-Lead SOIC_N Pin Configuration
NC = NO CONNECT
Figure 3. 16-Lead LFCSP_VQ Pin Configuration
Table 4. Pin Function Descriptions
SOIC_N 1 2 3 4 5 6 7 8 Pin No. LFCSP_VQ 2 4 6 8 10 12 13, 14 15, 16 1, 3, 5, 7, 9, 11 Mnemonic VDD DIGOUT DIGIN VNEG VPOS VCLAMP VOUT VSS DVSS, AVSS DVDD, AVDD NC Description Positive Supply Voltage. In read mode this pin functions as a digital output. Digital Input. Negative Amplifier Input (Inverting Input). Positive Amplifier Input (Noninverting Input). Set Clamp Voltage at Output. Amplifier Output. Negative Supply Voltage. Negative Supply Voltage. Positive Supply Voltage. Do Not Connect.
Rev. PrC | Page 7 of 19
NC 5 VNEG 6 NC 7 VPOS 8
AD8557 TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Input Offset Voltage Distribution
Preliminary Technical Data
www..com
Figure 21. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)
Figure 22. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz) Figure 5. Input Offset Voltage vs. Common-Mode Voltage
Figure 6. Input Offset Voltage vs. Temperature
Figure 23. Closed-Loop Gain vs. Frequency Measured at Filter Pin
Figure 7. TCVOS at VSY = 5 V Figure 24. Closed-Loop Gain vs. Frequency Measured at Output Pin
Figure 8. Output Buffer Offset vs. Temperature
Figure 25. Output Buffer Gain vs. Frequency
Figure 9. Input Bias Current at VPOS, VNEG vs. Temperature
Figure 26. Output Buffer Positive Overshoot
Figure 10. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage
Figure 27. Output Buffer Negative Overshoot
Figure 28. Output Voltage to Supply Rail vs. Load Current Figure 11. Input Offset Current vs. Temperature
Figure 29. Output Short-Circuit vs. Temperature Figure 12. Digital Input Current vs. Digital Input Voltage (Pin 4)
Figure 13. VCLAMP Current over Temperature at VS = 5 V vs. VCLAMP Voltage
Figure 30. Power-On Response at 25C
Figure 14. Supply Current (ISY) vs. Supply Voltage
Figure 31. Power-On Response at 125C
Figure 15. Supply Current (ISY) vs. Temperature
Figure 32. Power-On Response at -40C
Figure 16. CMRR vs. Frequency Figure 33. PSRR vs. Temperature Figure 17. CMRR vs. Frequency Figure 34. PSRR vs. Frequency
Figure 18. CMRR vs. Temperature at Different Gains Figure 35. Small Signal Response Figure 19. Input Voltage Noise Density vs. Frequency (0 Hz to 10 kHz) Figure 36. Small Signal Response Figure 20. Input Voltage Noise Density vs. Frequency (0 Hz to 500 kHz)
Rev. PrC | Page 8 of 19
Preliminary Technical Data
Figure 37. Large Signal Response
AD8557
www..com
Figure 43. Positive Overload Recovery (Gain = 1280)
Figure 38. Large Signal Response Figure 44. Settling Time 0.1%
Figure 39. Output Impedance vs. Frequency
Figure 45. Settling Time 0.01%
Figure 40. Negative Overload Recovery (Gain = 70)
Figure 46. THD vs. Frequency
Figure 41. Positive Overload Recovery (Gain = 70)
Figure 42. Negative Overload Recovery (Gain = 1280)
Rev. PrC | Page 9 of 19
AD8557 THEORY OF OPERATION
A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the differential amplifier. A1 and A2 are auto-zeroed op amps that minimize input offset errors. P1 and P2 are digital potentiometers, guaranteed to be monotonic. Programming P1 and P2 allows the first stage gain to be varied from 2.8 to 5.2 with 7-bit resolution (see Table 5 and Equation 1), giving a fine gain adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each have a similar temperature coefficient, so the first stage gain temperature coefficient is lower than 100 ppm/C.
Preliminary Technical Data
www..com
VDD. The input to A4, VCLAMP, has a very high input resistance. It should be connected to a known voltage and not left floating. However, the high input impedance allows the clamp voltage to be set using a high impedance source, such as, a potential divider. If the maximum value of VOUT does not need to be limited, VCLAMP should be connected to VDD. An 8-bit digital-to-analog converter (DAC) is used to generate a variable offset for the amplifier output. This DAC is guaranteed to be monotonic. To preserve the ratiometric nature of the input signal, the DAC references are driven from VSS and VDD, and the DAC output can swing from VSS (Code 0) to VDD (Code 255). The 8-bit resolution is equivalent to 0.39% of the difference between VDD and VSS, for example, 19.5 mV with a 5 V supply. The DAC output voltage (VDAC) is given approximately by
5.2 127 GAIN1 2.8 x 2.8
Code
(1)
A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the differential amplifier. A3 is an auto-zeroed op amp that minimizes input offset errors and also includes an output buffer. P3 and P4 are digital potentiometers, which allow the second stage gain to be varied from 10 to 250 in eight steps (see Table 6). R4, R5, R6, R7, P3, and P4 each have a similar temperature coefficient, so the second stage gain temperature coefficient is lower than 100 ppm/C. The output stage of A3 is supplied from a buffered version of VCLAMP instead of VDD, allowing the positive swing to be limited.
Code + 0.5 VDAC (VDD - VSS ) + VSS 256
(2)
Where the temperature coefficient of VDAC is lower than 200 ppm/C. The amplifier output voltage (VOUT) is given by
VOUT = GAIN (VPOS - VNEG ) + VDAC
(3)
where GAIN is the product of the first and second stage gains.
A4 implements a voltage buffer, which provides the positive supply to the output stage of A3. Its function is to limit VOUT to a maximum value, useful for driving analog-to-digital converters (ADC) operating on supply voltages lower than
{insert picture} Figure 47. Functional Schematic
Rev. PrC | Page 10 of 19
Preliminary Technical Data
GAIN VALUES
Table 5. First Stage Gain vs. First Stage Gain Code
First Stage Gain Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 First Stage Gain First Stage Gain Code 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 First Stage Gain First Stage Gain Code 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 First Stage Gain First Stage Gain Code 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
AD8557
www..com
First Stage Gain
Table 6. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code
Second Stage Gain Code 0 1 2 3 4 5 6 7 Second Stage Gain Minimum Combined Gain Maximum Combined Gain
Rev. PrC | Page 11 of 19
AD8557
OPEN WIRE FAULT DETECTION
The inputs to A1 and A2, VNEG and VPOS, each have a comparator to detect whether VNEG or VPOS exceeds a threshold voltage, nominally VDD - 2.0 V. If (VNEG > VDD - 2.0 V) or (VPOS > VDD - 2.0 V), VOUT is clamped to VSS. The output current limit circuit is disabled in this mode, but the maximum sink current is approximately 10 mA when VDD = 5 V. The inputs to A1 and A2, VNEG and VPOS, are also pulled up to VDD by currents IP1 and IP2. These are both nominally 49 nA and matched to within 3 nA. If the inputs to A1 or A2 are accidentally left floating, as with an open wire fault, IP1 and IP2 pull them to VDD which would cause VOUT to swing to VSS, allowing this fault to be detected. It is not possible to disable IP1 and IP2, nor the clamping of VOUT to VSS, when VNEG or VPOS approaches VDD.
Preliminary Technical Data
www..com
FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION
A floating fault condition at the VPOS, VNEG, or VCLAMP pins is detected by using a low current to pull a floating input into an error voltage range, defined in the previous section. In this way, the VOUT pin is shorted to VSS when a floating input is detected. Table 8 lists the currents used.
Table 8. Floating Fault Detection at VPOS, VNEG, and VCLAMP
Pin VPOS VNEG VCLAMP Typical Current 16 nA pull-up 16 nA pull-up 0.2 A pull-down Goal of Current Pull VPOS above VINH Pull VNEG above VINH Pull VCLAMP below VCLL
SHORTED WIRE FAULT DETECTION
The AD8557 provides fault detection in the case where VPOS, VNEG, or VCLAMP shorts to VDD and VSS. Figure 48 shows the voltage regions at VPOS, VNEG, and VCLAMP that trigger an error condition. When an error condition occurs, the VOUT pin is shorted to VSS. Table 7 lists the voltage levels shown in Figure 48.
VPOS VDD ERROR VINH ERROR VINH NORMAL NORMAL NORMAL
05448-048
DEVICE PROGRAMMING
Digital Interface
The digital interface allows the first stage gain, second stage gain, and output offset to be adjusted and allows desired values for these parameters to be permanently stored by selectively blowing polysilicon fuses. To minimize pin count and board space, a single-wire digital interface is used. The digital input pin, DIGIN, has hysteresis to minimize the possibility of inadvertent triggering with slow signals. It also has a pull-down current sink to allow it to be left floating when programming is not being performed. The pull-down ensures inactive status of the digital input by forcing a dc low voltage on DIGIN. A short pulse at DIGIN from low to high and back to low again, such as between 50 ns and 10 s long, loads a 0 into a shift register. A long pulse at DIGIN, such as 50 s or longer, loads a 1 into the shift register. The time between pulses should be at least 10 s. Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 x VDD are recognized as a low, and voltages at DIGIN between 0.8 x VDD and VDD are recognized as a high. A timing diagram example, Figure 49, shows the waveform for entering code 010011 into the shift register.
VNEG VDD
VCLAMP VDD
VCLL ERROR VINL VSS ERROR VINL VSS ERROR VSS
Figure 48. Voltage Regions at VPOS, VNEG, and VCLAMP that Trigger a Fault Condition
Table 7. Typical VINL, VINH, and VCLL Values (VDD = 5 V)
Voltage VINH VINL VCLL Min (V) 3.9 0.195 1.0 Max (V) 4.2 0.55 1.2 VOUT Condition Short to VSS fault detection Short to VSS fault detection Short to VSS fault detection
Rev. PrC | Page 12 of 19
Preliminary Technical Data
tW1 tWS tW0
WAVEFORM
AD8557
www..com
tWS tWS tW0 tW0 tWS tW1 tWS tW1
CODE
0
1
0
0
1
1
Figure 49. Timing Diagram for Code 010011
Table 9. Timing Specifications
Timing Parameter tw0 tw1 tws Description Pulse Width for Loading 0 into Shift Register Pulse Width for Loading 1 into Shift Register Width Between Pulses Specification Between 50 ns and 10 s 50 s 10 s
Table 10. 38-Bit Serial Word Format
Field No. 0 1 Bits 0 to 11 12 to 13 Description 12-Bit Start of Packet 1000 0000 0001 2-Bit Function 00: Change Sense Current 01: Simulate Parameter Value 10: Program Parameter Value 11: Read Parameter Value 2-Bit Parameter 00: Second Stage Gain Code 01: First Stage Gain Code 10: Output Offset Code 11: Other Functions 2-Bit Dummy 10 8-Bit Value Parameter 00 (Second Stage Gain Code): 3 LSBs Used Parameter 01 (First Stage Gain Code): 7 LSBs Used Parameter 10 (Output Offset Code): All 8 Bits Used Parameter 11 (Other Functions) Bit 0 (LSB): Master Fuse Bit 1: Fuse for Production Test at Analog Devices 12-Bit End of Packet 0111 1111 1110
2
14 to 15
3 4
16 to 17 18 to 25
5
26 to 37
A 38-bit serial word is used, divided into 6 fields. Assuming each bit can be loaded in 60 s, the 38-bit serial word transfers in 2.3 ms. Table 10 summarizes the word format. Field 0 and Field 5 are the start-of-packet field and end-ofpacket field, respectively. Matching the start-of-packet field with 1000 0000 0001 and the end-of-packet field with 0111 1111 1110 ensures that the serial word is valid and enables decoding of the other fields. Field 3 breaks up the data and ensures that no data combination can inadvertently trigger the start-of-packet and end-of-packet fields. Field 0 should be written first and Field 5 written last.
Within each field, the MSB must be written first and the LSB written last. The shift register features power-on reset to minimize the risk of inadvertent programming; power-on reset occurs when VDD is between 0.7 V and 2.2 V.
Rev. PrC | Page 13 of 19
05448-049
AD8557
Initial State
Initially, all the polysilicon fuses are intact. Each parameter has the value 0 assigned (see Table 11).
Table 11. Initial State Before Programming
Second Stage Gain Code = 0 First stage gain code = 0 Output offset code = 0 Master fuse = 0 Second Stage Gain = 17.5 First stage gain = 4.0 Output offset = VSS Master fuse not blown
Preliminary Technical Data
www..com
At least 10 F (tantalum type) of decoupling capacitance is needed across the power pins of the device during programming. The capacitance can be on the programming apparatus as long as it is within 2 inches of the device being programmed. An additional 0.1 F (ceramic type) in parallel with the 10 F is recommended within 1/2 inch of the device being programmed. A minimum period of 1 ms should be allowed for each fuse to blow. There is no need to measure the supply current during programming. The best way to verify correct programming is to use the read mode to read back the programmed values. Then, remeasure the gain and offset to verify these values. Programmed fuses have no effect on the gain and output offset until the master fuse is blown. After blowing the master fuse, the gain and output offset are determined solely by the blown fuses, and the simulation mode is permanently deactivated. Parameters are programmed by setting Field 1 to 10, selecting the desired parameter in Field 2, and selecting a single bit with the value 1 in Field 4. As an example, suppose the user wants to permanently set the second stage gain to 50. Parameter 00 needs to have the value 0000 0011 assigned. Two bits have the value 1, so two fuses need to be blown. Since only one fuse can be blown at a time, this code can be used to blow one fuse: 1000 0000 0001 10 00 10 0000 0010 0111 1111 1110 The MOS switch that blows the fuse closes when the complete packet is recognized, and opens when the start-of-packet, dummy, or end-of-packet fields are no longer valid. After 1 ms, this second code is entered to blow the second fuse: 1000 0000 0001 10 00 10 0000 0001 0111 1111 1110 To permanently set the first stage gain to a nominal value of 4.151, Parameter 01 needs to have the value 000 1011 assigned. Three fuses need to be blown, and the following codes are used, with a 1 ms delay after each code: 1000 0000 0001 10 01 10 0000 1000 0111 1111 1110 1000 0000 0001 10 01 10 0000 0010 0111 1111 1110 1000 0000 0001 10 01 10 0000 0001 0111 1111 1110 To permanently set the output offset to a nominal value of 1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs to have the value 0100 0000 assigned. If one fuse needs to be blown, use the following code: 1000 0000 0001 10 10 10 0100 0000 0111 1111 1110 Finally, to blow the master fuse to deactivate the simulation mode and prevent further programming, use code: 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110 There are a total of 20 programmable fuses. Since each fuse requires 1 ms to blow, and each serial word can be loaded in 2.3
When power is applied to a device, parameter values are taken either from internal registers, if the master fuse is not blown, or from the polysilicon fuses, if the master fuse is blown. Programmed values have no effect until the master fuse is blown. The internal registers feature power-on reset, so the unprogrammed devices enter a known state after power-up. Power-on reset occurs when VDD is between 0.7 V and 2.2 V.
Simulation Mode
The simulation mode allows any parameter to be temporarily changed. These changes are retained until the simulated value is reprogrammed, the power is removed, or the master fuse is blown. Parameters are simulated by setting Field 1 to 01, selecting the desired parameter in Field 2, and the desired value for the parameter in Field 4. Note that a value of 11 for Field 2 is ignored during the simulation mode. Examples of temporary settings follow:
* Setting the second stage gain code (Parameter 00) to 011 and the second stage gain to 50 produces: 1000 0000 0001 01 00 10 0000 0011 0111 1111 1110 * Setting the first stage gain code (Parameter 01) to 000 1011 and the first stage gain to 4.166 produces: 1000 0000 0001 01 01 10 0000 1011 0111 1111 1110
A first stage gain of 4.166 with a second stage gain of 50 gives a total gain of 208.3. This gain has a maximum tolerance of 2.5%.
* Set the output offset code (Parameter 10) to 0100 0000 and the output offset to 1.260 V when VDD = 5 V and VSS = 0 V. This output offset has a maximum tolerance of 0.8%: 1000 0000 0001 01 10 10 0100 0000 0111 1111 1110
Programming Mode
Intact fuses give a bit value of 0. Bits with a desired value of 1 need to have the associated fuse blown. Since a relatively large current is needed to blow a fuse, only one fuse can be reliably blown at a time. Thus, a given parameter value may need several 38-bit words to allow reliable programming. A 5.25 V (0.25 V) supply is required when blowing fuses to minimize the on resistance of the internal MOS switches that blow the fuse. The power supply voltage must not exceed the absolute maximum rating and must be able to deliver 250 mA of current.
Rev. PrC | Page 14 of 19
Preliminary Technical Data
ms, the maximum time needed to program the fuses can be as low as 66 ms.
AD8557
www..com
Read Mode
The values stored by the polysilicon fuses can be sent to the FILT/DIGOUT pin to verify correct programming. Normally, the FILT/DIGOUT pin is only connected to the second gain stage output via RF. During read mode, however, the FILT/DIGOUT pin is also connected to the output of a shift register to allow the polysilicon fuse contents to be read. Since VOUT is a buffered version of FILT/DIGOUT, VOUT also outputs a digital signal during read mode. Read mode is entered by setting Field 1 to 11 and selecting the desired parameter in Field 2. Field 4 is ignored. The parameter value, stored in the polysilicon fuses, is loaded into an internal shift register, and the MSB of the shift register is connected to the FILT/DIGOUT pin. Pulses at DIGIN shift out the shift register contents to the FILT/DIGOUT pin, allowing the 8bit parameter value to be read after seven additional pulses; shifting occurs on the falling edge of DIGIN. An eighth pulse at DIGIN disconnects FILT/DIGOUT from the shift register and terminates the read mode. If a parameter value is less than eight bits long, the MSBs of the shift register are padded with 0s. For example, to read the second stage gain, this code is used: 1000 0000 0001 11 00 10 0000 0000 0111 1111 1110 Since the second stage gain parameter value is only three bits long, the FILT/DIGOUT pin has a value of 0 when this code is entered, and remains 0 during four additional pulses at DIGIN. The fifth, sixth, and seventh pulses at DIGIN return the 3-bit value at FILT/DIGOUT, the seventh pulse returns the LSB. An eighth pulse at DIGIN terminates the read mode.
approximately 1.5 V could be developed across the fuse. Thus, the OTP cell could output Logic 0 or a Logic 1, depending on temperature, supply voltage, and other variables. To detect this undesirable situation, the sense current can be lowered by a factor of 4 using a specific code. The voltage developed across the fuse would then change from 1.5 V to 0.38 V, and the output of the OTP would be a Logic 0 instead of the expected Logic 1 from a blown fuse. Correctly blown fuses would still output a Logic 1. In this way, incorrectly blown fuses can be detected. Another specific code would return the sense current to the normal (larger) value. The sense current cannot be permanently programmed to the low value. When the AD8557 is powered up, the sense current defaults to the high value. The low sense current code is: 1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110 The normal (high) sense current code is: 1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110
Programming Procedure
For reliable fuse programming, it is imperative to follow the programming procedure requirements, especially the proper supply voltage during programming. 1. When programming the AD8557, the temperature of the device must be between 10C to 40C. 2. Set VDD and VSS to the desired values in the application. Use simulation mode to test and determine the desired codes for the second stage gain, first stage gain, and output offset. The nominal values for these parameters are shown in Table 5, Table 6, Equation 2, and Equation 3; use the codes corresponding to these values as a starting point. However, since actual parameter values for given codes vary from device to device, some fine tuning is necessary for the best possible accuracy. One way to choose these values is to set the output offset to an approximate value, such as Code 128 for midsupply, to allow the required gain to be determined. Then set the second stage gain so the minimum first stage gain (Code 0) gives a lower gain than required, and the maximum first stage gain (Code 127) gives a higher gain than required. After choosing the second stage gain, the first stage gain can be chosen to fine tune the total gain. Finally, the output offset can be adjusted to give the desired value. After determining the desired codes for second stage gain, first stage gain, and output offset, the device is ready for permanent programming.
Important: Once a programming attempt has been made for any fuse, there should be no further attempt to blow that fuse. If a fuse does not program to the expected state, discard
Sense Current
A sense current is sent across each polysilicon fuse to determine whether it has been blown. When the voltage across the fuse is less than approximately 1.5 V, the fuse is considered not blown, and Logic 0 is output from the OTP cell. When the voltage across the fuse is greater than approximately 1.5 V, the fuse is considered blown, and Logic 1 is output. When the AD8557 is manufactured, all fuses have a low resistance. When a sense current is sent through the fuse, a voltage less than 0.1 V is developed across the fuse. This is much lower than 1.5 V, so Logic 0 is output from the OTP cell. When a fuse is electrically blown, it should have a very high resistance. When the sense current is applied to the blown fuse, the voltage across the fuse should be larger than 1.5 V, so Logic 1 is output from the OTP cell. It is theoretically possible, though very unlikely, for a fuse to be incompletely blown during programming, assuming the required conditions are met. In this situation, the fuse could have a medium resistance, neither low nor high, and a voltage of
Rev. PrC | Page 15 of 19
AD8557
the unit. The expected incidence rate of attempted but unblown fuses is very small when following the proper programming procedure and conditions. 3. Set VSS to 0 V and VDD to 5.25 V (0.25 V). Power supplies should be capable of supplying 250 mA at the required voltage and properly bypassed as described in the Programming Mode section. Use program mode to permanently enter the desired codes for the first stage gain, second stage gain, and output offset. Blow the master fuse to allow the AD8557 to read data from the fuses and to prevent further programming. 4. Set VDD and VSS to the desired values in the application. Use read mode with low sense current followed by high sense current to verify programmed codes. 5. Measure gain and offset to verify correct functionality.
Preliminary Technical Data
www..com
4. Measure the resulting gain (GB). GB should be within 3% of GA. 5. Calculate the first stage gain error (in relative terms) EG1 = GB/GA - 1. 6. Calculate the error (in the number of the first stage gain codes) CEG1 = EG1/0.00370. 7. Set the first stage gain code to CG1 - CEG1. 8. Measure the gain (GC). GC should be closer to GA than to GB. 9. Calculate the error (in relative terms) EG2 = GC/GA - 1. 10. Calculate the error (in the number of the first stage gain codes) CEG2 = EG2/0.00370. 11. Set the first stage gain code to CG1 - CEG1 - CEG2. The resulting gain should be within one code of GA. Finally, determine the desired output offset: 1. Determine the desired output offset OA (using the measurements obtained from the simulation). 2. Use Equation 2 to set the output offset code CO1 such that the output offset is nominally OA. 3. Measure the output offset (OB). OB should be within 3% of OA. 4. Calculate the error (in relative terms) EO1 = OB/OA - 1. 5. Calculate the error (in the number of the output offset codes) CEO1 = EO1/0.00392. 6. Set the output offset code to CO1 - CEO1. 7. Measure the output offset (OC). OC should be closer to OA than to OB. 8. Calculate the error (in relative terms) EO2 = OC/OA - 1. 9. Calculate the error (in the number of the output offset codes) CEO2 = EO2/0.00392. 10. Set the output offset code to CO1 - CEO1 - CEO2. The resulting offset should be within one code of OA.
Determining Optimal Gain and Offset Codes
First, determine the desired gain: 1. Determine the desired gain, GA (using the measurements obtained from the simulation). 2. Use Table 6 to determine G2, the second stage gain, such that (4.00 x 1.04) < (GA/G2) < (6.4/1.04). This ensures the first and last codes for the first stage gain are not used, thereby allowing enough first stage gain codes within each second stage gain range to adjust for the 3% accuracy. Next, set the second stage gain: 1. Use the simulation mode to set the second stage gain to G2. 2. Set the output offset to allow the AD8557 gain to be measured, for example, use Code 128 to set it to midsupply. 3. Use Table 5 or Equation 1 to set the first stage gain code CG1, so the first stage gain is nominally GA/G2.
Rev. PrC | Page 16 of 19
Preliminary Technical Data OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5
AD8557
www..com
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440)
4 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
4.00 BSC SQ 0.60 MAX 0.60 MAX
13 12 16 1
PIN 1 INDICATOR 2.25 2.10 SQ 1.95 0.25 MIN 1.95 BSC
PIN 1 INDICATOR
TOP VIEW
0.65 BSC 3.75 BSC SQ 0.75 0.60 0.50
EXPOSED PAD
(BOTTOM VIEW)
9 8 5
4
12 MAX 1.00 0.85 0.80
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-16-4) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8557AR AD8557AR-REEL AD8557AR-REEL7 AD8557AR-EVAL AD8557ACP-R2 AD8557ACP-REEL AD8557ACP-REEL7 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC Evaluation Board 16-Lead LFCSP 16-Lead LFCSP 16-Lead LFCSP Package Option R-8 R-8 R-8 CP-16 CP-16 CP-16
Rev. PrC | Page 17 of 19
AD8557
Preliminary Technical Data
www..com
NOTES
Rev. PrC | Page 18 of 19
Preliminary Technical Data
AD8557
www..com
NOTES
(c)2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06013-0-5/06(PrC)
Rev. PrC | Page 19 of 19

▲Up To Search▲

Price & Availability of AD8557

	To Download AD8557 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .